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CVIU
2010
267views more  CVIU 2010»
13 years 2 months ago
Accelerated hardware video object segmentation: From foreground detection to connected components labelling
This paper demonstrates the use of a single-chip FPGA for the segmentation of moving objects in a video sequence. The system maintains highly accurate background models, and integ...
Kofi Appiah, Andrew Hunter, Patrick Dickinson, Hon...
FPL
2008
Springer
175views Hardware» more  FPL 2008»
13 years 6 months ago
File system access from reconfigurable FPGA hardware processes in BORPH
This paper presents the design and implementation of BORPH's kernel file system layer that provides FPGA processes direct access to the general file system. Using a semantics...
Hayden Kwok-Hay So, Robert W. Brodersen
CSREAESA
2006
13 years 6 months ago
Design and Implementation of SoPC with Multi-Bus on a Chip
SoPC (System on a Programmable Chip) is one important kind of SoC solution based on PLD (Programmable Logic Device). At the same time, PBD (Platform-based Design) has become popul...
Fangjun Jian, Jizhong Han, Chengde Han, Qin Zhang,...
AHS
2006
IEEE
195views Hardware» more  AHS 2006»
13 years 11 months ago
An Efficient Hardware Architecture for H.264 Adaptive Deblocking Filter
This paper presents an efficient hardware architecture for real-time implementation of adaptive deblocking filter algorithm used in H.264 video coding standard. This hardware is d...
Mustafa Parlak, Ilker Hamzaoglu
MJ
2006
145views more  MJ 2006»
13 years 5 months ago
A design flow for speeding-up dsp applications in heterogeneous reconfigurable systems
In this paper, we propose a method for speeding-up Digital Signal Processing applications by partitioning them between the reconfigurable hardware blocks of different granularity ...
Michalis D. Galanis, Athanasios Milidonis, Athanas...