15 search results - page 2 / 3 » FPGA Designs with Optimized Logarithmic Arithmetic |
ASAP
2008
IEEE
13 years 12 months ago
2008
IEEE
Many complex systems require the use of floating point arithmetic that is exceedingly time consuming to perform on personal computers. However, floating point operators are also h...
ARITH
1993
IEEE
13 years 9 months ago
1993
IEEE
This paper describes a logarithmic number system (LNS) arithmetic unit using a new methodfor polynomial interpolation in hardware. The use of an interleaved memory reduces storage...
IPPS
2005
IEEE
13 years 11 months ago
2005
IEEE
The use of pipelined floating-point arithmetic cores to create high-performance FPGA-based computational kernels has introduced a new class of problems that do not exist when usi...
DAC
2004
ACM
14 years 6 months ago
2004
ACM
A tool that automates the floating-point to fixed-point conversion (FFC) process for digital signal processing systems is described. The tool automatically optimizes fixed-point d...
ESTIMEDIA
2004
Springer
13 years 11 months ago
2004
Springer
We proposed a hardware accelerator IP for the Tier-1 portion of Embedded Block Coding with Optimal Truncation (EBCOT) used in the JPEG2000 next generation image compression standa...