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FPL
2006
Springer
137views Hardware» more  FPL 2006»
13 years 8 months ago
FPGA Performance Optimization Via Chipwise Placement Considering Process Variations
Both custom IC and FPGA designs in the nanometer regime suffer from process variations. But different from custom ICs, FPGAs' programmability offers a unique design freedom t...
Lerong Cheng, Jinjun Xiong, Lei He, Mike Hutton
FPGA
2010
ACM
250views FPGA» more  FPGA 2010»
14 years 1 months ago
Variation-aware placement for FPGAs with multi-cycle statistical timing analysis
Deep submicron processes have allowed FPGAs to grow in complexity and speed. However, such technology scaling has caused FPGAs to become more susceptible to the effects of process...
Gregory Lucas, Chen Dong, Deming Chen
FPGA
2009
ACM
233views FPGA» more  FPGA 2009»
13 years 11 months ago
FPCNA: a field programmable carbon nanotube array
Carbon nanotubes (CNTs), with their unique electronic properties, are promising materials for building nanoscale circuits. In this paper, we present a new CNT-based FPGA architect...
Chen Dong, Scott Chilstedt, Deming Chen
PODS
2005
ACM
128views Database» more  PODS 2005»
14 years 4 months ago
Operator placement for in-network stream query processing
In sensor networks, data acquisition frequently takes place at lowcapability devices. The acquired data is then transmitted through a hierarchy of nodes having progressively incre...
Utkarsh Srivastava, Kamesh Munagala, Jennifer Wido...
DAC
2009
ACM
13 years 11 months ago
Clock skew optimization via wiresizing for timing sign-off covering all process corners
Manufacturing process variability impacts the performance of synchronous logic circuits by means of its effect on both clock network and functional block delays. Typically, varia...
Sari Onaissi, Khaled R. Heloue, Farid N. Najm