44 search results - page 1 / 9 » FPGA Technology Mapping for Power Minimization |
FPL
1994
Springer
13 years 9 months ago
1994
Springer
FPGA
1995
ACM
13 years 9 months ago
1995
ACM
We study the nominal delay minimization problem in LUTbased FPGA technologymapping, where interconnect delay is assumed proportionalto net fanout size. We prove that the delay-opt...
FPGA
2004
ACM
13 years 10 months ago
2004
ACM
In this paper we study the technology mapping problem of FPGA architectures with dual supply voltages (Vdds) for power optimization. This is done with the guarantee that the mappi...
ICCAD
2004
IEEE
14 years 2 months ago
2004
IEEE
— This paper presents Hermes, a depth-optimal LUT based FPGA mapping algorithm. The presented algorithm is based on a new strategy for finding LUTs allowing to find a good LUT ...
DAC
2007
ACM
14 years 6 months ago
2007
ACM
In 90-nm technology, dynamic power is still the largest power source in FPGAs [1], and signal glitches contribute a large portion of the dynamic power consumption. Previous powera...