87 search results - page 1 / 18 » FPGA power reduction using configurable dual-Vdd |
DAC
2004
ACM
14 years 6 months ago
2004
ACM
Power optimization is of growing importance for FPGAs in nanometer technologies. Considering dual-Vdd technique, we show that configurable power supply is required to obtain a sat...
DAC
2006
ACM
14 years 6 months ago
2006
ACM
Field programmable dual-Vdd interconnects are effective to reduce FPGA power. Assuming uniform length interconnects, existing work has developed time slack budgeting to minimize p...
DAC
2005
ACM
2005
ACM
Leakage efficient chip-level dual-Vdd assignment with time slack allocation for FPGA power reduction
14 years 6 months ago
To reduce power, Vdd programmability has been proposed recently to select Vdd-level for interconnects and to powergate unused interconnects. However, Vdd-level converters used in ...
ISLPED
2004
ACM
13 years 10 months ago
2004
ACM
This paper presents a delay optimal FPGA clustering algorithm targeting low power. We assume that the configurable logic blocks of the FPGA can be programmed using either a high s...
ASPDAC
2006
ACM
13 years 11 months ago
2006
ACM
Extensive research has proposed the use of multiple on-die power supplies (VDD) for reducing power consumption in CMOS circuits. We present a detailed study and design techniques ...