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DAC
2004
ACM
13 years 9 months ago
Statistical gate delay model considering multiple input switching
There is an increased dominance of intra-die process variations, creating a need for an accurate and fast statistical timing analysis. Most of the recent proposed approaches assum...
Aseem Agarwal, Florentin Dartu, David Blaauw
SLIP
2009
ACM
13 years 12 months ago
Closed-form solution for timing analysis of process variations on SWCNT interconnect
In this paper, a comprehensive and fast method is presented for the timing analysis of process variations on single-walled carbon nanotube (SWCNT) bundles. Unlike previous works t...
Peng Sun, Rong Luo
ASPDAC
2010
ACM
165views Hardware» more  ASPDAC 2010»
13 years 3 months ago
Dynamic power estimation for deep submicron circuits with process variation
- Dynamic power consumption in CMOS circuits is usually estimated based on the number of signal transitions. However, when considering glitches, this is not accurate because narrow...
Quang Dinh, Deming Chen, Martin D. F. Wong
DATE
2010
IEEE
178views Hardware» more  DATE 2010»
13 years 10 months ago
Circuit propagation delay estimation through multivariate regression-based modeling under spatio-temporal variability
—With every process generation, the problem of variability in physical parameters and environmental conditions poses a great challenge to the design of fast and reliable circuits...
Shrikanth Ganapathy, Ramon Canal, Antonio Gonz&aac...
ASPDAC
2006
ACM
118views Hardware» more  ASPDAC 2006»
13 years 11 months ago
A probabilistic analysis of pipelined global interconnect under process variations
— The main thesis of this paper is to perform a reliability based performance analysis for a shared latch inserted global interconnect under uncertainty. We first put forward a ...
Navneeth Kankani, Vineet Agarwal, Janet Meiling Wa...