6 search results - page 1 / 2 » Fast Test Pattern Generation for Sequential Circuits Using D... |
ET
2000
13 years 4 months ago
2000
The paper presents a novel hierarchical approach to test pattern generation for sequential circuits based on an input model of mixed-level decision diagrams. A method that handles,...
DATE
1999
IEEE
13 years 9 months ago
1999
IEEE
A novel approach to testing sequential circuits that uses multi-level decision diagram representations is introduced. The proposed algorithm consists of a combination of scanning ...
DSD
2006
IEEE
13 years 10 months ago
2006
IEEE
Recently, a number of works have been published on implementing assignment decision diagram models combined with SAT methods to address register-transfer level test pattern genera...
EURODAC
1994
IEEE
13 years 8 months ago
1994
IEEE
This paper presents an algorithm for generation of test patterns for strong robust path delay faults, i.e. tests that propagate the fault along a single path and additionally are ...
CPAIOR
2007
Springer
13 years 10 months ago
2007
Springer
Abstract. In recent work binary decision diagrams (BDDs) were introduced as a technique for postoptimality analysis for integer programming. In this paper we show that much smaller...