8 search results - page 1 / 2 » Fast branch misprediction recovery in out-of-order superscal... |
ICS
2005
Tsinghua U.
13 years 10 months ago
2005
Tsinghua U.
ARCS
2010
Springer
13 years 9 months ago
2010
Springer
Register renaming is a widely used technique to remove false data dependencies in contemporary superscalar microprocessors. The register rename logic includes a mapping table that ...
MICRO
2008
IEEE
13 years 11 months ago
2008
IEEE
— Processor architectures with large instruction windows have been proposed to expose more instruction-level parallelism (ILP) and increase performance. Some of the proposed arch...
MICRO
1998
IEEE
13 years 9 months ago
1998
IEEE
We present an architecture that features dynamic multithreading execution of a single program. Threads are created automatically by hardware at procedure and loop boundaries and e...
CAL
2006
13 years 4 months ago
2006
This paper makes a case for using multi-core processors to simultaneously achieve transient-fault tolerance and performance enhancement. Our approach is extended from a recent late...