Because of the increasing dominance of interconnect issues in advanced IC technology, placement has become a critical step in the IC design flow. To get accurate interconnect inf...
Abstract-- In nanometer-scale VLSI technologies, several interconnect issues like routing congestion and interconnect delay have become the main concerns in placement. However, all...
The number of vias generated during the global routing stage is a critical factor for the yield of final circuits. However, most global routers only approach the problem by chargin...
In this paper, we present a hierarchical ratio partitioning based placement algorithm for large-scale mixed-size designs. The placement algorithm consists of three steps: global p...
—This paper presents an efficient technique for the estimation of the routed wirelength during global placement using the wire density of the net. The proposed method identifie...