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TCAD
1998
86views more  TCAD 1998»
13 years 5 months ago
Fast heuristic and exact algorithms for two-level hazard-free logic minimization
None of the available minimizers for 2-level hazard-free logic minimization can synthesize very large circuits. This limitation has forced researchers to resort to manual and auto...
Michael Theobald, Steven M. Nowick
DAC
1997
ACM
13 years 10 months ago
Multilevel Hypergraph Partitioning: Application in VLSI Domain
In this paper, we present a new hypergraph partitioning algorithm that is based on the multilevel paradigm. In the multilevel paradigm, a sequence of successively coarser hypergra...
George Karypis, Rajat Aggarwal, Vipin Kumar, Shash...
JPDC
2000
141views more  JPDC 2000»
13 years 5 months ago
A System for Evaluating Performance and Cost of SIMD Array Designs
: SIMD arrays are likely to become increasingly important as coprocessors in domain specific systems as architects continue to leverage RAM technology in their design. The problem ...
Martin C. Herbordt, Jade Cravy, Renoy Sam, Owais K...
BIOINFORMATICS
2010
127views more  BIOINFORMATICS 2010»
13 years 6 months ago
Analyzing taxonomic classification using extensible Markov models
Motivation: As next generation sequencing is rapidly adding new genomes, their correct placement in the taxonomy needs verification. However, the current methods for confirming cl...
Rao M. Kotamarti, Michael Hahsler, Douglas Raiford...
ISCAS
2005
IEEE
191views Hardware» more  ISCAS 2005»
13 years 11 months ago
Behavioural modeling and simulation of a switched-current phase locked loop
Recent work has shown that the use of switched current methods can provide an effective route to implementation of analog IC functionality using a standard digital CMOS process. Fu...
Peter R. Wilson, Reuben Wilcock