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» Fault Diagnosis in Integrated Circuits with BIST
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GLVLSI
2005
IEEE
118views VLSI» more  GLVLSI 2005»
13 years 10 months ago
High-diagnosability online built-in self-test of FPGAs via iterative bootstrapping
We develop a novel on-line built-in self-test (BIST) technique for testing FPGAs that has a very high diagnosability even in presence of clustered faults, a fault pattern for whic...
Vishal Suthar, Shantanu Dutt
DSD
2007
IEEE
98views Hardware» more  DSD 2007»
13 years 11 months ago
Fault Diagnosis in Integrated Circuits with BIST
This paper presents an optimized fault diagnosing procedure applicable in Built-in Self-Test environments. Instead of the known approach based on a simple bisection of patterns in...
Raimund Ubar, Sergei Kostin, Jaan Raik, Teet Evart...
IOLTS
2006
IEEE
101views Hardware» more  IOLTS 2006»
13 years 10 months ago
Delay Fault Localization in Test-Per-Scan BIST Using Built-In Delay Sensor
— Delay failures are becoming a dominant failure mechanism in nanometer technologies. Diagnosis of such failures is important to ensure yield and robustness of the design. Howeve...
Swaroop Ghosh, Swarup Bhunia, Arijit Raychowdhury,...
ETS
2011
IEEE
220views Hardware» more  ETS 2011»
12 years 4 months ago
Structural In-Field Diagnosis for Random Logic Circuits
—In-field diagnosability of electronic components in larger systems such as automobiles becomes a necessity for both customers and system integrators. Traditionally, functional ...
Alejandro Cook, Melanie Elm, Hans-Joachim Wunderli...
ITC
2003
IEEE
149views Hardware» more  ITC 2003»
13 years 10 months ago
On Reducing Aliasing Effects and Improving Diagnosis of Logic BIST Failures
Diagnosing failing vectors in a Built-In Self Test (BIST) environment is a difficult task because of the highly compressed signature coming out of the Multiple Input Shift Regist...
Ramesh C. Tekumalla