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» Fault Pattern Oriented Defect Diagnosis for Memories
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ITC
2003
IEEE
139views Hardware» more  ITC 2003»
13 years 10 months ago
Fault Pattern Oriented Defect Diagnosis for Memories
Failure analysis (FA) and diagnosis of memory cores plays a key role in system-on-chip (SOC) product development and yield ramp-up. Conventional FA based on bitmaps and the experi...
Chih-Wea Wang, Kuo-Liang Cheng, Jih-Nung Lee, Yung...
ATS
2009
IEEE
117views Hardware» more  ATS 2009»
13 years 11 months ago
N-distinguishing Tests for Enhanced Defect Diagnosis
Diagnostic ATPG has traditionally been used to generate test patterns that distinguish pairs of modeled faults. In this work, we investigate the use of n-distinguishing test sets,...
Gang Chen, Janusz Rajski, Sudhakar M. Reddy, Irith...
EAAI
2010
130views more  EAAI 2010»
13 years 4 months ago
Fault diagnosis in railway track circuits using Dempster-Shafer classifier fusion
This paper addresses the problem of fault detection and isolation in railway track circuits. A track circuit can be considered as a large-scale system composed of a series of trim...
Latifa Oukhellou, Alexandra Debiolles, Thierry Den...
DATE
2009
IEEE
94views Hardware» more  DATE 2009»
13 years 11 months ago
Improving compressed test pattern generation for multiple scan chain failure diagnosis
To reduce test data volumes, encoded tests and compacted test responses are widely used in industry. Use of test response compaction negatively impacts fault diagnosis since the e...
Xun Tang, Ruifeng Guo, Wu-Tung Cheng, Sudhakar M. ...
ATS
2009
IEEE
135views Hardware» more  ATS 2009»
13 years 11 months ago
On Scan Chain Diagnosis for Intermittent Faults
Diagnosis is increasingly important, not only for individual analysis of failing ICs, but also for high-volume test response analysis which enables yield and test improvement. Sca...
Dan Adolfsson, Joanna Siew, Erik Jan Marinissen, E...