13 search results - page 1 / 3 » Fault diagnosis in scan-based BIST using both time and space... |
ITC
1999
IEEE
13 years 10 months ago
1999
IEEE
DATE
2002
IEEE
13 years 10 months ago
2002
IEEE
A gate level, automated fault diagnosis scheme is proposed for scan-based BIST designs. The proposed scheme utilizes both fault capturing scan chain information and failing test v...
ICCAD
2002
IEEE
14 years 2 months ago
2002
IEEE
We present a new method of built-in-self-test (BIST) for sequential circuits and system-on-a-chip (SOC) using characteristic faults and circuitspeciļ¬c spectral information in th...
DATE
1999
IEEE
13 years 10 months ago
1999
IEEE
In this paper, new and efficient BIST methodology and BIST hardware insertion algorithms are presented for RTL data paths obtained from high level synthesis. The methodology is ba...
IOLTS
2002
IEEE
13 years 10 months ago
2002
IEEE
This paper proposes a new solution for the diagnosis of faults into embedded RAMs, currently under evaluation within STMicroelectronics. The proposed scheme uses dedicated circuit...