32 search results - page 2 / 7 » Fault modeling and simulation for crosstalk in system-on-chi... |
SLIP
2006
ACM
13 years 11 months ago
2006
ACM
Crosstalk aggressor alignment induces significant interconnect delay variation and needs to be taken into account in a statistical timer. In this paper, we approximate crosstalk ...
VLSID
2002
IEEE
14 years 5 months ago
2002
IEEE
Interconnection networks in Systems-On-Chip begin to have a non-negligible impact on the power consumption of a whole system. This is because of increasing inter-wire capacitances...
DATE
2003
IEEE
13 years 10 months ago
2003
IEEE
Circuit marginality failures in high performance VLSI circuits are projected to increase due to shrinking process geometries and high frequency design techniques. Capacitive cross...
ASPDAC
2005
ACM
13 years 7 months ago
2005
ACM
－ We propose a novel oscillation ring (OR) test architecture for testing interconnects in SoC. In addition to stuck-at and open faults, this scheme can detect delay faults and cr...
DAC
2002
ACM
14 years 6 months ago
2002
ACM
Rapid approximation of the transient response of high-speed global interconnects is needed to estimate the time delay, crosstalk, and overshoot in a GSI multilevel wiring network....