51 search results - page 2 / 11 » Feedback mechanisms for improving probabilistic memory prefe... |
MICRO
2010
IEEE
13 years 3 months ago
2010
IEEE
Abstract-- We consider the problem of how to improve memory latency tolerance in massively multithreaded GPGPUs when the thread-level parallelism of an application is not sufficien...
ICPP
2003
IEEE
13 years 10 months ago
2003
IEEE
Aggressive hardware-based and software-based prefetch algorithms for hiding memory access latencies were proposed to bridge the gap of the expanding speed disparity between proces...
HPCA
2003
IEEE
14 years 5 months ago
2003
IEEE
Although caches for decades have been the backbone of the memory system, the speed gap between CPU and main memory suggests their augmentation with prefetching mechanisms. Recentl...
MICRO
2009
IEEE
14 years 1 days ago
2009
IEEE
DRAM systems achieve high performance when all DRAM banks are busy servicing useful memory requests. The degree to which DRAM banks are busy is called DRAM Bank-Level Parallelism ...
ISCA
2011
IEEE
12 years 9 months ago
2011
IEEE
Chip multiprocessors (CMPs) share a large portion of the memory subsystem among multiple cores. Recent proposals have addressed high-performance and fair management of these share...