This paper describes the concept, architecture, development and demonstration of a real time, high performance, software defined 4-receiver system and a space time decoder to be i...
In this paper, we study the incremental t echnology mapping problem for lookup-table (LUT) based Field Programmable Gate Arrays (FPGAs) under incremental changes. Given a gate-lev...
The results of fast implementations of all five AES final candidates using Virtex Xilinx Field Programmable Gate Arrays are presented and analyzed. Performance of several alternati...
—To construct 3D virtual scenes from two-dimensional images with depth information, image warping techniques could be used. In this paper, a novel approach of cylindrical depth i...
This paper presents a methodology for production-time testing of (uncustomized) segmented channel eld programmable gate arrays (FPGAs) such as those manufactured by Actel [1]. Th...