56 search results - page 3 / 12 » FinFETs for nanoscale CMOS digital integrated circuits |
VLSID
2007
IEEE
14 years 5 months ago
2007
IEEE
As technology scales to 40nm and beyond, intra-die process variability will cause large delay and leakage variations across a chip in addition to expected die-to-die variations. I...
ITC
1996
IEEE
13 years 9 months ago
1996
IEEE
A novel approach to testing CMOS digital circuits is presented that is based on an analysis of IDD switching transients on the supply rails and voltage transients at selected test...
DATE
2006
IEEE
13 years 11 months ago
2006
IEEE
For CMOS technologies below 65nm, gate oxide direct tunneling current is a major component of the total power dissipation. This paper presents a simulated annealing based algorith...
MICRO
2006
IEEE
13 years 5 months ago
2006
IEEE
Shrinking devices to the nanoscale, increasing integration densities, and reducing of voltage levels down to the thermal limit, all conspire to produce faulty systems. Frequent oc...
DAC
2009
ACM
14 years 6 months ago
2009
ACM
In this study, we apply a novel synthesis technique for implementing robust digital computation in nanoscale lattices with random interconnects: percolation theory on random graph...