3 search results - page 1 / 1 » Finding the Worst Voltage Violation in Multi-Domain Clock Ga... |
DATE
2008
IEEE
13 years 11 months ago
2008
IEEE
This paper proposes an efficient method to find the worst case of voltage violation by multi-domain clock gating in an on-chip power network. We first present a voltage response i...
SLIP
2009
ACM
13 years 11 months ago
2009
ACM
This paper proposes an efficient method to predict the worst case of voltage violation by multi-domain clock gating in a three-dimensional (3D) on-chip power network considering l...
ISLPED
2004
ACM
13 years 10 months ago
2004
ACM
Microprocessor designers use techniques such as clock gating to reduce power dissipation. An unfortunate side-effect of these techniques is the processor current fluctuations th...