A novel design approach for simultaneous power and stability (static noise margin, SNM) optimization of nanoCMOS static random access memory (SRAM) is presented. A 45nm single-end...
Garima Thakral, Saraju P. Mohanty, Dhruva Ghai, Dh...
Soft errors that change configuration bits of an SRAM based FPGA modify the functionality of the design. The proliferation of FPGA devices in various critical applications makes it...
Suresh Srinivasan, Aman Gayasen, Narayanan Vijaykr...
The on-chip memory is a dominant source of power and energy consumption in modern and future processors. This paper explores the use of a new emerging non-volatile memory technolo...
Straining of silicon improves mobility of carriers resulting in speed enhancement for transistors in CMOS technology. Traditionally, silicon straining is applied in a similar ad-h...