Sciweavers

6 search results - page 1 / 2
» Fine-grain leakage optimization in SRAM based FPGAs
Sort
View
GLVLSI
2005
IEEE
81views VLSI» more  GLVLSI 2005»
13 years 11 months ago
Fine-grain leakage optimization in SRAM based FPGAs
Somsubhra Mondal, Seda Ogrenci Memik
VLSID
2010
IEEE
211views VLSI» more  VLSID 2010»
13 years 9 months ago
A Combined DOE-ILP Based Power and Read Stability Optimization in Nano-CMOS SRAM
A novel design approach for simultaneous power and stability (static noise margin, SNM) optimization of nanoCMOS static random access memory (SRAM) is presented. A 45nm single-end...
Garima Thakral, Saraju P. Mohanty, Dhruva Ghai, Dh...
ICCAD
2004
IEEE
85views Hardware» more  ICCAD 2004»
14 years 2 months ago
Improving soft-error tolerance of FPGA configuration bits
Soft errors that change configuration bits of an SRAM based FPGA modify the functionality of the design. The proliferation of FPGA devices in various critical applications makes it...
Suresh Srinivasan, Aman Gayasen, Narayanan Vijaykr...
ISLPED
2010
ACM
229views Hardware» more  ISLPED 2010»
13 years 5 months ago
An energy efficient cache design using spin torque transfer (STT) RAM
The on-chip memory is a dominant source of power and energy consumption in modern and future processors. This paper explores the use of a new emerging non-volatile memory technolo...
Mitchelle Rasquinha, Dhruv Choudhary, Subho Chatte...
ISQED
2007
IEEE
136views Hardware» more  ISQED 2007»
13 years 11 months ago
Strain Silicon Optimization for Memory and Logic in Nano-Scale CMOS
Straining of silicon improves mobility of carriers resulting in speed enhancement for transistors in CMOS technology. Traditionally, silicon straining is applied in a similar ad-h...
Rajani Kuchipudi, Hamid Mahmoodi