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EH
2003
IEEE
138views Hardware» more  EH 2003»
13 years 10 months ago
Implementing Evolution of FIR-Filters Efficiently in an FPGA
Reconfigurable hardware devices make it possible to change the topology of electronic circuits at runtime. Using reconfigurable devices as a platform for Evolvable hardware (EHW) ...
Knut Arne Vinger, Jim Torresen
ISPD
2005
ACM
239views Hardware» more  ISPD 2005»
13 years 11 months ago
Mapping algorithm for large-scale field programmable analog array
Modern advances in reconfigurable analog technologies are allowing field-programmable analog arrays (FPAAs) to dramatically grow in size, flexibility, and usefulness. With thes...
I. Faik Baskaya, Sasank Reddy, Sung Kyu Lim, Tyson...
EURODAC
1994
IEEE
209views VHDL» more  EURODAC 1994»
13 years 9 months ago
MOS VLSI circuit simulation by hardware accelerator using semi-natural models
- The accelerator is destined to circuit-level simulation of digital and analog/digital MOS VLSI'c containing of up to 100 thousand transistors (with 16 Mb RAM host-machine). ...
Victor V. Denisenko
ERSA
2009
147views Hardware» more  ERSA 2009»
13 years 3 months ago
Fault Avoidance in Medium-Grain Reconfigurable Hardware Architectures
Medium-grain reconfigurable hardware (MGRH) architectures represent a hybrid between the versatility of a field programmable gate array (FPGA) and the computational power of a cust...
Kylan Robinson, José G. Delgado-Frias
ISLPED
1995
ACM
112views Hardware» more  ISLPED 1995»
13 years 9 months ago
Ultra-low-power analog associative memory core using flash-EEPROM-based programmable capacitors
Analog techniques can lead to ultra-efficient computational systems when applied to the right applications. The problem of associative memory is well suited to array-based analog ...
Alan Kramer, Roberto Canegallo, Mauro Chinosi, D. ...