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» Floorplanning in Modern FPGAs
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VLSID
2007
IEEE
92views VLSI» more  VLSID 2007»
14 years 5 months ago
Floorplanning in Modern FPGAs
State-of-the-art FPGA architectures have millions of gates in CLBs, Block RAMs, and Multiplier blocks which can host fairly large designs. While their physical design calls for oor...
Pritha Banerjee, Susmita Sur-Kolay, Arijit Bishnu
DAC
2009
ACM
14 years 6 months ago
Handling complexities in modern large-scale mixed-size placement
In this paper, we propose an effective algorithm flow to handle largescale mixed-size placement. The basic idea is to use floorplanning to guide the placement of objects at the gl...
Jackey Z. Yan, Natarajan Viswanathan, Chris Chu
ISPD
2005
ACM
143views Hardware» more  ISPD 2005»
13 years 10 months ago
Modern floorplanning based on fast simulated annealing
Tung-Chieh Chen, Yao-Wen Chang
VLSID
2009
IEEE
142views VLSI» more  VLSID 2009»
14 years 5 months ago
Floorplanning for Partial Reconfiguration in FPGAs
Partial Reconfiguration on heterogeneous Field Programmable Gate Arrays (FPGA) with millions of gates yields better utilization of resources by swapping in and out the active modu...
Pritha Banerjee, Megha Sangtani, Susmita Sur-Kolay
ASPDAC
2004
ACM
120views Hardware» more  ASPDAC 2004»
13 years 10 months ago
Temporal floorplanning using 3D-subTCG
Improving logic capacity by time-sharing, dynamically reconfigurable FPGAs are employed to handle designs of high complexity and functionality. In this paper, we use a novel topo...
Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang, Hsin-...