Sciweavers

15 search results - page 1 / 3
» Flow Graph Balancing for Minimizing the Required Memory Band...
Sort
View
ISSS
1996
IEEE
114views Hardware» more  ISSS 1996»
13 years 9 months ago
Flow Graph Balancing for Minimizing the Required Memory Bandwidth
In this paper we present the problem of flow graph balancing for minimizingthe required memory bandwidth. Our goal is to minimize the required memory bandwidth within the given cy...
Sven Wuytack, Francky Catthoor, Gjalt G. de Jong, ...
DAC
2012
ACM
11 years 7 months ago
A QoS-aware memory controller for dynamically balancing GPU and CPU bandwidth use in an MPSoC
Diverse IP cores are integrated on a modern system-on-chip and share resources. Off-chip memory bandwidth is often the scarcest resource and requires careful allocation. Two of t...
Min Kyu Jeong, Mattan Erez, Chander Sudanthi, Nige...
ISCA
2002
IEEE
174views Hardware» more  ISCA 2002»
13 years 4 months ago
Efficient Task Partitioning Algorithms for Distributed Shared Memory Systems
In this paper, we consider the tree task graphs which arise from many important programming paradigms such as divide and conquer, branch and bound etc., and the linear task-graphs...
Sibabrata Ray, Hong Jiang
SIGARCH
2008
94views more  SIGARCH 2008»
13 years 4 months ago
Optimized on-chip pipelining of memory-intensive computations on the cell BE
Multiprocessors-on-chip, such as the Cell BE processor, regularly suffer from restricted bandwidth to off-chip main memory. We propose to reduce memory bandwidth requirements, and...
Christoph W. Kessler, Jörg Keller
LCN
2005
IEEE
13 years 10 months ago
Rate-based Flow-control for the CICQ Switch
A combined input and crosspoint queued (CICQ) switch with a flow control latency of round-trip time (RTT) packets requires each crosspoint (CP) buffer to hold the RTT packets in o...
Kenji Yoshigoe