7 search results - page 1 / 2 » Formal Verification for High-Assurance Behavioral Synthesis |
ATVA
2009
Springer
13 years 8 months ago
2009
Springer
We present a framework for certifying hardware designs generated through behavioral synthesis, by using formal verification to certify the associated synthesis transformations. We ...
ICCAD
2002
IEEE
14 years 1 months ago
2002
IEEE
In this paper we present an advanced functional extraction tool for automatic generation of high-level RTL from switch-level circuit netlist representation. The tool is called FEV...
CORR
2008
Springer
13 years 4 months ago
2008
Springer
Synchronous languages rely on formal methods to ease the development of applications in an efficient and reusable way. Formal methods have been advocated as a means of increasing t...
FMCAD
2007
Springer
13 years 8 months ago
2007
Springer
Modeling hardware through atomic guard/action transitions with interleaving semantics is popular, owing to the conceptual clarity of modeling and verifying the high level behavior ...
VLSID
2008
IEEE
14 years 5 months ago
2008
IEEE
Protocol conversion involves the use of a converter to control communication between two or more protocols such that desired system-level specifications can be satisfied. We invest...