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» Functional Test Generation for FSMs by Fault Extraction
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ASPDAC
2005
ACM
107views Hardware» more  ASPDAC 2005»
13 years 6 months ago
Constraint extraction for pseudo-functional scan-based delay testing
Recent research results have shown that the traditional structural testing for delay and crosstalk faults may result in over-testing due to the non-trivial number of such faults t...
Yung-Chieh Lin, Feng Lu, Kai Yang, Kwang-Ting Chen...
PTS
1993
91views Hardware» more  PTS 1993»
13 years 6 months ago
Generating Tests for Control Portion of SDL Specifications
The signal SAVE construct is one of the features distinguishing SDL from convent specification and programming languages. On the other hand, this feature increase testing SDL-spec...
Gang Luo, Anindya Das, Gregor von Bochmann
DATE
2000
IEEE
121views Hardware» more  DATE 2000»
13 years 9 months ago
Functional Test Generation for Full Scan Circuits
We study the effectiveness of functional tests for full scan circuits. Functional tests are important for design validation, and they potentially have a high defect coverage indep...
Irith Pomeranz, Sudhakar M. Reddy
ATS
2003
IEEE
131views Hardware» more  ATS 2003»
13 years 10 months ago
Software-Based Delay Fault Testing of Processor Cores
Software-based self-testing is a promising approach for the testing of processor cores which are embedded inside a System-on-a-Chip (SoC), as it can apply test vectors in function...
Virendra Singh, Michiko Inoue, Kewal K. Saluja, Hi...
DFT
2002
IEEE
127views VLSI» more  DFT 2002»
13 years 9 months ago
A New Functional Fault Model for FPGA Application-Oriented Testing
1 The objective of this paper is to propose a new fault model suitable for test pattern generation for an FPGA configured to implement a given application. The paper demonstrates t...
Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo ...