Sciweavers

142 search results - page 1 / 29
» Functional test generation for non-scan sequential circuits
Sort
View
EURODAC
1995
IEEE
164views VHDL» more  EURODAC 1995»
13 years 9 months ago
Bottleneck removal algorithm for dynamic compaction and test cycles reduction
: We present a new, dynamic algorithm for test sequence compaction and test cycle reduction for combinationaland sequential circuits. Several dynamic algorithms for compaction in c...
Srimat T. Chakradhar, Anand Raghunathan
DATE
1999
IEEE
111views Hardware» more  DATE 1999»
13 years 9 months ago
Sequential Circuit Test Generation Using Decision Diagram Models
A novel approach to testing sequential circuits that uses multi-level decision diagram representations is introduced. The proposed algorithm consists of a combination of scanning ...
Jaan Raik, Raimund Ubar
ICCD
2006
IEEE
105views Hardware» more  ICCD 2006»
13 years 11 months ago
A New Class of Sequential Circuits with Acyclic Test Generation Complexity
—This paper introduces a new class of sequential circuits called acyclically testable sequential circuits which is wider than the class of acyclic sequential circuits but whose t...
Chia Yee Ooi, Hideo Fujiwara
VLSID
1995
IEEE
107views VLSI» more  VLSID 1995»
13 years 9 months ago
Functional test generation for non-scan sequential circuits
Mandyam-Komar Srinivas, James Jacob, Vishwani D. A...