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DATE
2000
IEEE
142views Hardware» more  DATE 2000»
13 years 9 months ago
Power and Delay Reduction via Simultaneous Logic and Placement Optimization in FPGAs
Traditional FPGA design flows have treated logic synthesis and physical design as separate steps. With the recent advances in technology, the lack of information on the physical ...
Balakrishna Kumthekar, Fabio Somenzi
ISMVL
2003
IEEE
112views Hardware» more  ISMVL 2003»
13 years 10 months ago
Iterative Symmetry Indices Decomposition for Ternary Logic Synthesis in Three-Dimensional Space
This paper introduces the implementation of the Iterative Symmetry Indices Decomposition (ISID) for the synthesis of ternary threedimensional logic circuits. The synthesis of regu...
Anas Al-Rabadi
FPL
2005
Springer
114views Hardware» more  FPL 2005»
13 years 10 months ago
Post-Placement BDD-Based Decomposition for FPGAs
This work explores the effect of adding a timing driven functional decomposition step to the traditional field programmable gate array (FPGA) CAD flow. Once placement has comple...
Valavan Manohararajah, Deshanand P. Singh, Stephen...
FPL
1999
Springer
147views Hardware» more  FPL 1999»
13 years 9 months ago
Synthia: Synthesis of Interacting Automata Targeting LUT-based FPGAs
This paper details the development, implementation, and results of Synthia, a system for the synthesis of Finite State Machines (FSMs) to field-programmable logic. Our approach us...
George A. Constantinides, Peter Y. K. Cheung, Wayn...