20 search results - page 2 / 4 » Gate Sizing For Cell Library-Based Designs |
ICCAD
2003
IEEE
14 years 2 months ago
2003
IEEE
The recent past has seen a tremendous increase in the size of design circuits that can be implemented in a single FPGA. These large design sizes significantly impact cycle time du...
DAC
1999
ACM
14 years 6 months ago
1999
ACM
We propose a method for power optimization that considers glitch reduction by gate sizing based on the statistical estimation of glitch transitions. Our method reduces not only th...
GLVLSI
2006
IEEE
13 years 11 months ago
2006
IEEE
In this paper we have applied statistical sizing in an industrial setting. Efficient implementation of the statistical sizing algorithm is achieved by utilizing a dedicated interi...
ARITH
2007
IEEE
13 years 11 months ago
2007
IEEE
An emerging nanotechnology, quantum-dot cellular automata (QCA), has the potential for attractive features such as faster speed, smaller size, and lower power consumption than tra...
ICCAD
1995
IEEE
13 years 8 months ago
1995
IEEE
ng certain electrical noise and power constraints.Abstract: We present a new delay model for use in logic synthesis. A traditional model treats the area of a library cell as consta...