8 search results - page 1 / 2 » Gate sizing for crosstalk reduction under timing constraints... |
ICCAD
2004
IEEE
14 years 2 months ago
2004
IEEE
Abstract— This paper presents a post-route, timingconstrained gate-sizing algorithm for crosstalk reduction. Gate-sizing has emerged as a practical and feasible method to reduce ...
ICCAD
1998
IEEE
13 years 9 months ago
1998
IEEE
This paper considers simultaneous gate and wire sizing for general very large scale integrated (VLSI) circuits under the Elmore delay model. We present a fast and exact algorithm w...
TCAD
2008
13 years 5 months ago
2008
We present an efficient optimization scheme for gate sizing in the presence of process variations. Our method is a worst-case design scheme, but it reduces the pessimism involved i...
ASPDAC
2008
ACM
13 years 7 months ago
2008
ACM
Power dissipation is quickly becoming one of the most important limiters in nanometer IC design for leakage increases exponentially as the technology scaling down. However, power ...
ICDCS
1999
IEEE
13 years 9 months ago
1999
IEEE
To provide real-time service or engineer constrained-based paths, networks require the underlying routing algorithm to be able to find low-cost paths that satisfy given Quality-of...