36 search results - page 2 / 8 » Gate sizing for large cell-based designs |
SIGECOM
2010
ACM
13 years 9 months ago
2010
ACM
We designed and built the Gates Hillman Prediction Market (GHPM) to predict the opening day of the Gates and Hillman Centers, the new computer science buildings at Carnegie Mellon...
ICCAD
2003
IEEE
14 years 1 months ago
2003
IEEE
The recent past has seen a tremendous increase in the size of design circuits that can be implemented in a single FPGA. These large design sizes significantly impact cycle time du...
IEAAIE
1999
Springer
13 years 9 months ago
1999
Springer
This paper introduces a new approach in the debugging of hardware designs. The design is given as a VHDL program and converted in a component connection model. The conversion is si...
ITC
1999
IEEE
13 years 9 months ago
1999
IEEE
This paper discusses practical issues involved in applying logic built-in self-test (BIST) to four large industrial designs. These multi-clock designs, ranging in size from 200K t...
VLSID
2003
IEEE
14 years 5 months ago
2003
IEEE
In the previous work, the problem of nding gate delays to eliminate glitches has been solved by linear programs (LP) requiring an exponentially large number ofconstraints. By intr...