18 search results - page 3 / 4 » Gate sizing using incremental parameterized statistical timi... |
VLSID
2005
IEEE
14 years 6 months ago
2005
IEEE
This paper employs general multivariate normal distribution to develop a new efficient statistical timing analysis methodology. The paper presents the theoretical framework of the...
DAC
2005
ACM
13 years 8 months ago
2005
ACM
In this paper, we propose a new sensitivity based, statistical gate sizing method. Since circuit optimization effects the entire shape of the circuit delay distribution, it is dif...
GLVLSI
2010
IEEE
13 years 8 months ago
2010
IEEE
In this paper, we present an approved linear-time algorithm for statistical leakage analysis in the present of any spatial correlation condition (strong or weak). The new algorith...
ISQED
2007
IEEE
14 years 16 days ago
2007
IEEE
In nanometer regime, the effects of variations are having an increasing impact on the delay and power characteristics of devices as well as the yield of the circuit. Statistical t...
MICRO
2007
IEEE
14 years 16 days ago
2007
IEEE
Technology scaling, characterized by decreasing feature size, thinning gate oxide, and non-ideal voltage scaling, will become a major hindrance to microprocessor reliability in fu...