Sciweavers

268 search results - page 3 / 54
» Gating currents
Sort
View
ASPDAC
2005
ACM
92views Hardware» more  ASPDAC 2005»
13 years 8 months ago
Sleep transistor sizing using timing criticality and temporal currents
— Power gating is a circuit technique that enables high performance and low power operation. One of the challenges in power gating is sizing the sleep transistor which is used to...
Anand Ramalingam, Bin Zhang, Anirudh Devgan, David...
ASPDAC
2004
ACM
126views Hardware» more  ASPDAC 2004»
13 years 11 months ago
High-level area and power-up current estimation considering rich cell library
— Reducing the ever-growing leakage power is critical to power efficient designs. Leakage reduction techniques such as power-gating using sleep transistor insertion introduces la...
Fei Li, Lei He, Joseph M. Basile, Rakesh J. Patel,...
JCNS
2002
62views more  JCNS 2002»
13 years 5 months ago
Computing Transient Gating Charge Movement of Voltage-Dependent Ion Channels
The opening of voltage-gated sodium, potassium, and calcium ion channels has a steep relationship with voltage. In response to changes in the transmembrane voltage, structural move...
Anthony Varghese, Linda M. Boland
DATE
2008
IEEE
125views Hardware» more  DATE 2008»
14 years 15 days ago
Current source based standard cell model for accurate signal integrity and timing analysis
— The inductance and coupling effects in interconnects and non-linear receiver loads has resulted in complex input signals and output loads for gates in the modern deep submicron...
Amit Goel, Sarma B. K. Vrudhula
VLSID
2002
IEEE
107views VLSI» more  VLSID 2002»
14 years 6 months ago
Estimation of Maximum Power-Up Current
Power gating is emerging as a viable solution to reduction of leakage current. However, power gated circuits are different from the conventional designs in the sense that a power-...
Fei Li, Lei He, Kewal K. Saluja