8 search results - page 1 / 2 » Generalized Early Evaluation in Self-Timed Circuits |
DATE
2002
IEEE
13 years 9 months ago
2002
IEEE
Phased logic has been proposed as a technique for realizing self-timed circuitry that is delay-insensitive and requires no global clock signals. Early evaluation techniques have b...
DAC
2007
ACM
14 years 5 months ago
2007
ACM
A protocol for latency-insensitive design with early evaluation is presented. The protocol is based on a symmetric view of the system in which tokens carrying information move in ...
ASPDAC
2006
ACM
2006
ACM
Equivalent circuit modeling of guard ring structures for evaluation of substrate crosstalk isolation
13 years 10 months ago
— A substrate-coupling equivalent circuit can be derived for an arbitrary guard ring test structure by way of F-matrix computation. The derived netlist represents a unified impe...
HIS
2003
13 years 6 months ago
2003
Ant-based clustering and sorting is a nature-inspired heuristic for general clustering tasks. It has been applied variously, from problems arising in commerce, to circuit design, t...
DAC
2003
ACM
14 years 5 months ago
2003
ACM
Early power analysis for systems-on-chip (SoC) is crucial for determining the appropriate packaging and cost. This early analysis commonly relies on evaluating power formulas for ...