14 search results - page 1 / 3 » Generalized constraint generation in the presence of non-det... |
ICCAD
1996
IEEE
13 years 10 months ago
1996
IEEE
In a constraint-drivenlayout synthesisenvironment,parasitic constraints are generated and implemented in each phase of the design process to meet a given set of performance specif...
DAC
1996
ACM
13 years 10 months ago
1996
ACM
A novel methodology for circuit design and automatic layout generation is proposed for a class of mixed-signal circuits in presence of layout parasitics and substrate induced nois...
ISQED
2000
IEEE
2000
IEEE
A Layout Approach for Electrical and Physical Design Integration of High-Performance Analog Circuits
13 years 10 months ago
This paper presents a layout generation tool that aims to reduce the gap between electrical sizing and physical realization of high performance analog circuits. The procedural lay...
RTCSA
2000
IEEE
13 years 10 months ago
2000
IEEE
With the advance of applications such as multimedia, imagelspeech processing and real-time AI, real-time computing models allowing to express the “timeliness versus precision”...
CODES
2004
IEEE
13 years 9 months ago
2004
IEEE
Register bypassing is a powerful and widely used feature in modern processors to eliminate certain data hazards. Although complete bypassing is ideal for performance, bypassing ha...