1140 search results - page 2 / 228 » Generating compilers for generated datapaths |
TVLSI
2008
13 years 5 months ago
2008
Most hardware compilers apply loop pipelining to increase the parallelism achieved, but pipelining is restricted to the only innermost level in a nested loop. In this work we exten...
ISSS
2002
IEEE
13 years 10 months ago
2002
IEEE
Datapath width optimization is very effective for reducing the area of a custom-made embedded system. The trivial way of optimization is to iteratively customize, evaluate, and r...
TACO
2008
13 years 5 months ago
2008
r acceptance of FPGAs as a computing device requires a higher level of programming abstraction. ROCCC is an optimizing C to HDL compiler. We describe the code generation approach i...
FCCM
2000
IEEE
13 years 9 months ago
2000
IEEE
Mapping computations written in high-level programming languages to FPGA-based computing engines requires programmers to generate the datapath responsible for the core of the comp...
DAC
2000
ACM
13 years 9 months ago
2000
ACM
Datapath design is one of the most critical elements in the design of a high performance microprocessor. However datapath design is typically done manually, and is often custom st...