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TCAD
2002
106views more  TCAD 2002»
13 years 5 months ago
Design of hierarchical cellular automata for on-chip test pattern generator
This paper introduces the concept of hierarchical cellular automata (HCA). The theory of HCA is developed over the Galois extension field (2 ), where each cell of the CA can store ...
Biplab K. Sikdar, Niloy Ganguly, Parimal Pal Chaud...
DAC
2007
ACM
14 years 6 months ago
Transition Delay Fault Test Pattern Generation Considering Supply Voltage Noise in a SOC Design
Due to shrinking technology, increasing functional frequency and density, and reduced noise margins with supply voltage scaling, the sensitivity of designs to supply voltage noise...
Nisar Ahmed, Mohammad Tehranipoor, Vinay Jayaram
VTS
1998
IEEE
88views Hardware» more  VTS 1998»
13 years 9 months ago
Transition Maximization Techniques for Enhancing the Two-Pattern Fault Coverage of Pseudorandom Test Pattern Generators
This paper presents simulation evidence supporting the use of bit transition maximization techniques in the design of hardware test pattern generators TPGs. Bit transition maximiz...
Bruce F. Cockburn, Albert L.-C. Kwong
IJON
2007
118views more  IJON 2007»
13 years 5 months ago
Low power CMOS electronic central pattern generator design for a biomimetic underwater robot
— This paper, presents a feasability study of a central pattern generator-based analog controller for an autonomous robot. The operation of a neuronal circuit formed of electroni...
Young-Jun Lee, Jihyun Lee, Kyung Ki Kim, Yong-Bin ...
ATS
2009
IEEE
99views Hardware» more  ATS 2009»
14 years 6 days ago
Test Generation for Designs with On-Chip Clock Generators
High performance designs often use the on-chip device PLLs for accurate test clock generation during testing. The on-chip clock generator is designed in a programmable way to faci...
Xijiang Lin, Mark Kassab