41 search results - page 1 / 9 » Glitch Analysis and Reduction in Register Transfer Level |
DAC
1996
ACM
13 years 9 months ago
1996
ACM
: We presentdesign-for-low-power techniques based on glitch reduction for register-transfer level circuits. We analyze the generation and propagation of glitches in both the contro...
ICCAD
1996
IEEE
13 years 9 months ago
1996
IEEE
We present techniques for estimating switching activity and power consumption in register-transfer level (RTL) circuits. Previous work on this topic has ignored the presence of gl...
DFT
2007
IEEE
13 years 11 months ago
2007
IEEE
Decreasing feature sizes have led to an increased vulnerability of random logic to soft errors. A particle strike may cause a glitch or single event transient (SET) at the output ...
ICTAI
2002
IEEE
13 years 10 months ago
2002
IEEE
In order to reduce the time-to-market and simplify gatelevel test generation for digital integrated circuits, GAbased functional test generation techniques are proposed for behavi...
IPPS
2006
IEEE
13 years 11 months ago
2006
IEEE
Modern network processors support high levels of parallelism in packet processing by supporting multiple threads that execute on a micro-engine. Threads switch context upon encoun...