41 search results - page 8 / 9 » Glitch Analysis and Reduction in Register Transfer Level |
DAC
2003
ACM
13 years 11 months ago
2003
ACM
This paper presents an analytical framework for the implementation of digital infinite impulse response filters in fixed-point hardware on field programmable gate arrays. This ana...
DAC
2000
ACM
14 years 7 months ago
2000
ACM
Continuous scaling of VLSI circuits is reducing gate delays but rapidly increasing interconnect delays. Semiconductor Industry Association (SIA) roadmap predicts that, beyond the ...
RAID
1999
Springer
13 years 10 months ago
1999
Springer
We approached this line of inquiry by questioning the conventional wisdom that audit logs are too large to be analyzed and must be reduced and filtered before the data can be anal...
DAC
2005
ACM
14 years 7 months ago
2005
ACM
The challenge of verifying a modern microprocessor design is an overwhelming one: Increasingly complex micro-architectures combined with heavy time-to-market pressure have forced ...
CODES
2005
IEEE
13 years 11 months ago
2005
IEEE
The continuous improvement on the design methodologies and processes has made possible the creation of huge and very complex digital systems. Design verification is one of the mai...