8 search results - page 1 / 2 » Hand-in-hand verification of high-level synthesis |
FDL
2007
IEEE
13 years 11 months ago
2007
IEEE
SystemVerilog encapsulates both design description and verification properties in one language and provides a unified environment for engineers who have the formidable challenge o...
VLSID
2009
IEEE
14 years 5 months ago
2009
IEEE
: The challenges in nano-CMOS circuit design include the following: variability, leakage, power, thermals, reliability, and yield. This talk will focus on interdependent considerat...
VLSID
2006
IEEE
13 years 10 months ago
2006
IEEE
This tutorial present the key aspects of design challenges and its solutions that are being experienced in VLSI design in the era of nano technology. The focus will be on design c...
FMCAD
2007
Springer
13 years 8 months ago
2007
Springer
Modeling hardware through atomic guard/action transitions with interleaving semantics is popular, owing to the conceptual clarity of modeling and verifying the high level behavior ...
JSS
2010
12 years 11 months ago
2010
Architectural description languages are a useful tool for modeling complex systems at a high level of abstraction. If based on formal methods, they can also serve for enabling the...