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EUROMICRO
1999
IEEE
13 years 9 months ago
Design Space Exploration in System Level Synthesis under Memory Constraints
This paper addresses the problem of component selection, task assignment and task scheduling for distributed embedded computer systems. Such systems have a large number of constra...
Radoslaw Szymanek, Krzysztof Kuchcinski
ATS
2001
IEEE
126views Hardware» more  ATS 2001»
13 years 8 months ago
Design of an Optimal Test Access Architecture Using a Genetic Algorithm
Test access is a major problem for core-based systemon-chip (SOC) designs. Since cores in an SOC are not directly accessible via chip inputs and outputs, special access mechanisms...
Zahra Sadat Ebadi, André Ivanov
ISSS
2000
IEEE
109views Hardware» more  ISSS 2000»
13 years 8 months ago
FDRA: A Software-Pipelining Algorithm for Embedded VLIW Processors
The paper presents a novel software-pipelining algorithm suitable for optimizing compilers targeting embedded VLIW processors. The proposed algorithm is different from previous ap...
Cagdas Akturan, Margarida F. Jacome
DATE
2008
IEEE
114views Hardware» more  DATE 2008»
13 years 11 months ago
Synthesis of Fault-Tolerant Embedded Systems
This work addresses the issue of design optimization for faulttolerant hard real-time systems. In particular, our focus is on the handling of transient faults using both checkpoin...
Petru Eles, Viacheslav Izosimov, Paul Pop, Zebo Pe...
DT
2006
180views more  DT 2006»
13 years 5 months ago
A SystemC Refinement Methodology for Embedded Software
process: Designers must define higher abstraction levels that allow system modeling. They must use description languages that handle both hardware and software components to descri...
Jérôme Chevalier, Maxime de Nanclas, ...