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» Hardware Acceleration of HMMER on FPGAs
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IVC
2006
123views more  IVC 2006»
13 years 6 months ago
Multi-sector algorithm for hardware acceleration of the general Hough transform
The Multi-Sector Algorithm (MSA) is a simplification of the CORDIC algorithm to more closely meet the requirements for a real-time general Hough transform applications. The MSA ca...
Emeric K. Jolly, Martin Fleury
FCCM
2005
IEEE
89views VLSI» more  FCCM 2005»
13 years 11 months ago
A General Purpose, Highly Efficient Communication Controller Architecture for Hardware Acceleration Platforms
Although researchers have presented individual techniques to efficiently utilize the Peripheral Component Interconnect (PCI) bus, their contributions fail to provide a direct path...
Petersen F. Curt, James P. Durbano, Fernando E. Or...
FCCM
2009
IEEE
106views VLSI» more  FCCM 2009»
13 years 10 months ago
Optimal Placement-aware Trace-Based Scheduling of Hardware Reconfigurations for FPGA Accelerators
Modern use of FPGAs as hardware accelerators involves the partial reconfiguration of hardware resources as the application executes. In this paper, we present a polynomial time al...
Joon Edward Sim, Weng-Fai Wong, Jürgen Teich
FPL
2010
Springer
267views Hardware» more  FPL 2010»
13 years 4 months ago
A Comparison of Hardware Acceleration Interfaces in a Customizable Soft Core Processor
Due to the continuously decreasing cost of FPGAs, they have become a valid implementation platform for SOCs. Typically, a soft core processor implementation is used to execute the ...
Gerald Hempel, Christian Hochberger, Andreas Koch
CISS
2008
IEEE
14 years 15 days ago
Accelerated costas array enumeration using FPGAs
Abstract— Costas array enumeration is an NP-complete problem with a highly parallelize-able solution. This paper examines the implementation of a solution to this problem on an F...
Jim Devlin, Scott Rickard