112 search results - page 2 / 23 » Hardware Acceleration of Matrix Multiplication on a Xilinx F... |
FPL
2003
Springer
13 years 10 months ago
2003
Springer
This paper describes the implementation of the L3 maze routing accelerator in an FPGA. L3 supports fast single-layer and multi-layer routing, preferential routing, and rip-up-and-r...
FCCM
1998
IEEE
13 years 9 months ago
1998
IEEE
One of the major overheads in reconfigurable computing is the time it takes to reconfigure the devices in the system. This overhead limits the speedups possible in this exciting n...
FPGA
2005
ACM
13 years 10 months ago
2005
ACM
Floating-point Sparse Matrix-Vector Multiplication (SpMXV) is a key computational kernel in scientific and engineering applications. The poor data locality of sparse matrices sig...
FPL
2005
Springer
13 years 10 months ago
2005
Springer
This paper presents a DES/3DES core that will support Cipher Block Chaining (CBC) and also has a built in keygen that together take up about 10% of the resources in a Xilinx Virte...
SASP
2009
IEEE
13 years 12 months ago
2009
IEEE
—This paper presents a parallelized architecture for hardware acceleration of multi-view face detection. In our architecture, the multi-view face detection system generates rotat...