112 search results - page 3 / 23 » Hardware Acceleration of Matrix Multiplication on a Xilinx F... |
ARC
2012
Springer
12 years 1 months ago
2012
Springer
As the size of FPGA devices grows following Moore’s law, it becomes possible to put a complete manycore system onto a single FPGA chip. The centralized memory hierarchy on typica...
FPGA
2009
ACM
14 years 1 months ago
2009
ACM
This paper presents a hardware architecture for face detection based system on AdaBoost algorithm using Haar features. We describe the hardware design techniques including image s...
TC
2008
13 years 6 months ago
2008
Numerical linear algebra operations are key primitives in scientific computing. Performance optimizations of such operations have been extensively investigated. With the rapid adva...
FPL
2008
Springer
13 years 7 months ago
2008
Springer
In recent years the financial world has seen an increasing demand for faster risk simulations, driven by growth in client portfolios. Traditionally many financial models employ Mo...
IPPS
2003
IEEE
13 years 11 months ago
2003
IEEE
ShareStreams (Scalable Hardware Architectures for Stream Schedulers) is a canonical architecture for realizing a range of scheduling disciplines. This paper discusses the design c...