68 search results - page 13 / 14 » Hardware Scheduling for Dynamic Adaptability using External ... |
MICRO
2008
IEEE
13 years 11 months ago
2008
IEEE
Existing DRAM controllers employ rigid, non-adaptive scheduling and buffer management policies when servicing prefetch requests. Some controllers treat prefetch requests the same ...
ISCA
2005
IEEE
13 years 11 months ago
2005
IEEE
The load-store unit is a performance critical component of a dynamically-scheduled processor. It is also a complex and non-scalable component. Several recently proposed techniques...
EUROSYS
2010
ACM
14 years 2 months ago
2010
ACM
Bugs in concurrent programs are extremely difficult to find and fix during testing. In this paper, we propose Kivati, which can efficiently detect and prevent atomicity violat...
IPPS
2006
IEEE
13 years 11 months ago
2006
IEEE
The performance requirements for contemporary microprocessors are increasing as rapidly as their number of applications grows. By accelerating the clock, performance can be gained...
CODES
2007
IEEE
13 years 11 months ago
2007
IEEE
Memory requirements of intellectual property components (IP) in contemporary multi-processor systems-on-chip are increasing. Large high-speed external memories, such as DDR2 SDRAM...