Sciweavers

139 search results - page 4 / 28
» Hardware Software Instruction Set Configurability for System...
Sort
View
CASES
2008
ACM
13 years 7 months ago
VESPA: portable, scalable, and flexible FPGA-based vector processors
While soft processors are increasingly common in FPGAbased embedded systems, it remains a challenge to scale their performance. We propose extending soft processor instruction set...
Peter Yiannacouras, J. Gregory Steffan, Jonathan R...
DAC
1992
ACM
13 years 9 months ago
High Level Synthesis of Pipelined Instruction Set Processors and Back-End Compilers
Designing instruction set processors and constructing their compilers are mutually dependent tasks. Piper is a high level synthesis tool of ADAS which controls the hardware-softwa...
Ing-Jer Huang, Alvin M. Despain
ASAP
2000
IEEE
102views Hardware» more  ASAP 2000»
13 years 9 months ago
A Theory for Software-Hardware Co-Scheduling for ASIPs and Embedded Processors
Exploiting instruction-level parallelism (ILP) is extremely important for achieving high performance in application specific instruction set processors (ASIPs) and embedded proces...
Ramaswamy Govindarajan, Erik R. Altman, Guang R. G...
IPPS
2000
IEEE
13 years 9 months ago
Augmenting Modern Superscalar Architectures with Configurable Extended Instructions
The instruction sets of general-purpose microprocessors are designed to offer good performance across a wide range of programs. The size and complexity of the instruction sets, how...
Xianfeng Zhou, Margaret Martonosi
DAC
1996
ACM
13 years 9 months ago
A Hardware/Software Partitioning Algorithm for Designing Pipelined ASIPs with Least Gate Counts
Abstract -- This paper introduces a new HW/SW partitioning algorithm used in automating the instruction set processor design for pipelined ASIP (Application Specific Integrated Pro...
Nguyen-Ngoc Bình, Masaharu Imai, Akichika S...