25 search results - page 2 / 5 » HiDRA - A reactive multiprocessor architecture for heterogen... |
ICIP
1999
IEEE
14 years 6 months ago
1999
IEEE
A new chip-set for video display processing in a consumer television or set-top box is presented. Key aspect of the chip-set is a high flexibility and programmability of multi-win...
DATE
2003
IEEE
13 years 10 months ago
2003
IEEE
Software implementations of channel decoding algorithms are attractive for communication systems with their large variety of existing and emerging standards due to their flexibil...
DATE
2009
IEEE
13 years 11 months ago
2009
IEEE
—The sustained push for performance, transistor count, and instruction level parallelism has reached a point where chip level power density issues are at the forefront of design ...
DAC
2004
ACM
14 years 5 months ago
2004
ACM
As multiprocessor systems-on-chip become a reality, performance modeling becomes a challenge. To quickly evaluate many architectures, some type of high-level simulation is require...
CODES
2004
IEEE
13 years 8 months ago
2004
IEEE
Single chip heterogeneous multiprocessors are arising to meet the computational demands of portable and handheld devices. These computing systems are not fully custom designs trad...