11 search results - page 2 / 3 » Hiding Communication Latency with Non-SPMD, Graph-Based Exec... |
FPL
2006
Springer
13 years 8 months ago
2006
Springer
With current FPGAs, designers can now instantiate several embedded processors, memory units, and a wide variety of IP blocks to build a single-chip, high-performance multiprocesso...
IEEEPACT
2005
IEEE
13 years 10 months ago
2005
IEEE
Hiding communication latency is an important optimization for parallel programs. Programmers or compilers achieve this by using non-blocking communication primitives and overlappi...
ISCA
2003
IEEE
13 years 10 months ago
2003
IEEE
To address the increasing susceptibility of commodity chip multiprocessors (CMPs) to transient faults, we propose Chiplevel Redundantly Threaded multiprocessor with Recovery (CRTR...
HPCA
2011
IEEE
12 years 8 months ago
2011
IEEE
Future CMPs will combine many simple cores with deep cache hierarchies. With more cores, cache resources per core are fewer, and must be shared carefully to avoid poor utilization...
MICRO
1997
IEEE
13 years 9 months ago
1997
IEEE
Compiler optimizations are often driven by specific assumptions about the underlying architecture and implementation of the target machine. For example, when targeting shared-mem...