12 search results - page 3 / 3 » Hiding Synchronization Delays in a GALS Processor Microarchi... |
ISCA
2002
IEEE
13 years 10 months ago
2002
IEEE
Many emerging processor microarchitectures seek to manage technological constraints (e.g., wire delay, power, and circuit complexity) by resorting to nonuniform designs that provi...
DAC
2000
ACM
14 years 6 months ago
2000
ACM
Memory delays represent a major bottleneck in embedded systems performance. Newer memory modules exhibiting efficient access modes (e.g., page-, burst-mode) partly alleviate this ...