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» Hierarchical Test Generation with Built-In Fault Diagnosis
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ITC
2003
IEEE
168views Hardware» more  ITC 2003»
13 years 11 months ago
Agent Based DBIST/DBISR And Its Web/Wireless Management
This paper presents an attempt of using intelligent agents for testing and repairing a distributed system, whose elements may or may not have embedded BIST (Built-In Self-Test) an...
Liviu Miclea, Szilárd Enyedi, Gavril Todere...
CSREAESA
2009
13 years 6 months ago
Embedded Processor Based Fault Injection and SEU Emulation for FPGAs
Two embedded processor based fault injection case studies are presented which are applicable to Field Programmable Gate Arrays (FPGAs) and FPGA cores in configurable System-on-Chip...
Bradley F. Dutton, Mustafa Ali, Charles E. Stroud,...
ETS
2009
IEEE
117views Hardware» more  ETS 2009»
13 years 3 months ago
A Two Phase Approach for Minimal Diagnostic Test Set Generation
We optimize the full-response diagnostic fault dictionary from a given test set. The smallest set of vectors is selected without loss of diagnostic resolution of the given test se...
Mohammed Ashfaq Shukoor, Vishwani D. Agrawal
ICES
2000
Springer
140views Hardware» more  ICES 2000»
13 years 9 months ago
Evolving Cellular Automata for Self-Testing Hardware
Testing is a key issue in the design and production of digital circuits: the adoption of BIST (Built-In Self-Test) techniques is increasingly popular, but requires efficient algori...
Fulvio Corno, Matteo Sonza Reorda, Giovanni Squill...
ISCAS
1999
IEEE
106views Hardware» more  ISCAS 1999»
13 years 10 months ago
Test pattern generation for width compression in BIST
The main objectives of Built-In Self Test (BIST) are the design of test pattern generator circuits which achieve the highest fault coverage, require the shortest sequence of test ...
Paulo F. Flores, Horácio C. Neto, K. Chakra...