5 search results - page 1 / 1 » Hierarchical extraction of 3D interconnect capacitances in l... |
ICCAD
1993
IEEE
13 years 8 months ago
1993
IEEE
For submicron integrated circuits, 3D numerical techniques are required to accurately compute the values of the interconnect capacitances. In this paper, we describe an hierarchic...
ASPDAC
1999
ACM
13 years 9 months ago
1999
ACM
: In VLSI circuits with deep sub-micron, the parasitic capacitance from interconnect is a very important factor determining circuit performances such as power and time-delay. The B...
ICCAD
2009
IEEE
13 years 2 months ago
2009
IEEE
With the adoption of ultra regular fabric paradigms for controlling design printability at the 22nm node and beyond, there is an emerging need for a layout-driven, pattern-based p...
GLVLSI
2005
IEEE
13 years 10 months ago
2005
IEEE
This paper discusses interconnect capacitance extraction for system LCD circuits, where coupling capacitance is much significant since a ground plane locates far away unlike LSI ...
IPPS
2002
IEEE
13 years 9 months ago
2002
IEEE
Accurate estimation of signal delay is critical to the design and verification of VLSI circuits. At very high frequencies, signal delay in circuits with small feature sizes is do...