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» High Density Through Silicon Via (TSV)
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CORR
2008
Springer
194views Education» more  CORR 2008»
13 years 5 months ago
Fabrication of 3D Packaging TSV using DRIE
Emerging 3D chips stacking and MEMS/Sensors packaging technologies are using DRIE (Deep Reactive Ion Etching) to etch Through-Silicon Via (TSV) for advanced interconnections. The ...
M. Puech, Jean-Marc Thevenoud, J. M. Gruffat, N. L...
VLSI
2010
Springer
13 years 3 months ago
Design and feasibility of multi-Gb/s quasi-serial vertical interconnects based on TSVs for 3D ICs
—This paper proposes a novel technique to exploit the high bandwidth offered by through silicon vias (TSVs). In the proposed approach, synchronous parallel 3D links are replaced ...
Fengda Sun, Alessandro Cevrero, Panagiotis Athanas...
CORR
2008
Springer
94views Education» more  CORR 2008»
13 years 5 months ago
Through Silicon Vias as Enablers for 3D Systems
This special session on 3D TSV
E. Jung, Andreas Ostmann, Peter Ramm, Jürgen ...
ICCAD
2010
IEEE
146views Hardware» more  ICCAD 2010»
13 years 3 months ago
Through-silicon-via management during 3D physical design: When to add and how many?
In 3D integrated circuits through silicon vias (TSVs) are used to connect different dies stacked on top of each other. These TSV occupy silicon area and have significantly larger a...
Mohit Pathak, Young-Joon Lee, Thomas Moon, Sung Ky...
DAC
2010
ACM
13 years 9 months ago
TSV stress aware timing analysis with applications to 3D-IC layout optimization
As the geometry shrinking faces severe limitations, 3D wafer stacking with through silicon via (TSV) has gained interest for future SOC integration. Since TSV fill material and s...
Jae-Seok Yang, Krit Athikulwongse, Young-Joon Lee,...